Computer Science > Hardware Architecture
arXiv:2603.08724 (cs)
[Submitted on 17 Feb 2026]
Title:PhD Thesis Summary: Methods for Reliability Assessment and Enhancement of Deep Neural Network Hardware Accelerators
Authors:Mahdi Taheri
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Abstract:This manuscript summarizes the work and showcases the impact of the doctoral thesis by introducing novel, cost-efficient methods for assessing and enhancing the reliability of DNN hardware accelerators. A comprehensive Systematic Literature Review (SLR) was conducted, categorizing existing reliability assessment techniques, identifying research gaps, and leading to the development of new analytical reliability assessment tools. Additionally, this work explores the interplay between reliability, quantization, and approximation, proposing methodologies that optimize the trade-offs between computational efficiency and fault tolerance. Furthermore, a real-time, zero-overhead reliability enhancement technique, AdAM, was developed, providing fault tolerance comparable to traditional redundancy methods while significantly reducing hardware costs. The impact of this research extends beyond academia, contributing to multiple funded projects, masters courses, industrial collaborations, and the development of new tools and methodologies for efficient and reliable DNN hardware accelerators.
| Subjects: | Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Distributed, Parallel, and Cluster Computing (cs.DC) |
| Cite as: | arXiv:2603.08724 [cs.AR] |
| (or arXiv:2603.08724v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2603.08724
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