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Breaking the Tuning Barrier: Zero-Hyperparameters Yield Multi-Corner Analysis Via Learned Priors

arXiv cs.LG / 3/16/2026

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Key Points

  • The study introduces a zero-tuning method for cross-corner circuit analysis by leveraging learned priors from a foundation model trained on millions of regression tasks, enabling instant adaptation to each circuit.
  • It validates circuits across 25+ Process-Voltage-Temperature corners with a combinatorial simulation cost of O(K×N) and reduces total validation cost by over 10x compared with tuning-based approaches.
  • The approach replaces engineered priors with learned priors and uses in-context learning, with an attention mechanism that transfers knowledge across corners by identifying shared circuit physics under different operating conditions.
  • An automated feature selector reduces dimensionality from 1152D to 48D, while achieving state-of-the-art accuracy (mean MRE as low as 0.11%) without any tuning.
  • The results suggest a potential shift in EDA toolchains and design workflows by breaking the tuning barrier and enabling faster, more robust multi-corner analysis.

Abstract

Yield Multi-Corner Analysis validates circuits across 25+ Process-Voltage-Temperature corners, resulting in a combinatorial simulation cost of O(K \times N) where K denotes corners and N exceeds 10^4 samples per corner. Existing methods face a fundamental trade-off: simple models achieve automation but fail on nonlinear circuits, while advanced AI models capture complex behaviors but require hours of hyperparameter tuning per design iteration, forming the Tuning Barrier. We break this barrier by replacing engineered priors (i.e., model specifications) with learned priors from a foundation model pre-trained on millions of regression tasks. This model performs in-context learning, instantly adapting to each circuit without tuning or retraining. Its attention mechanism automatically transfers knowledge across corners by identifying shared circuit physics between operating conditions. Combined with an automated feature selector (1152D to 48D), our method matches state-of-the-art accuracy (mean MREs as low as 0.11\%) with zero tuning, reducing total validation cost by over 10\times.