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VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation

arXiv cs.CL / 3/11/2026

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Key Points

  • The study empirically analyzes how different language models interact with prompt engineering techniques for Verilog code generation.
  • It evaluates a range of models, including general-purpose, reasoning-focused, and domain-specific language models, using a controlled factorial design with various prompt styles and optimization strategies.
  • Experiments reveal patterns in how different model classes respond to structured prompts and prompt optimization, shedding light on which behaviors generalize across models and benchmarks.
  • The research highlights the trade-offs between model capabilities and prompt design in the specialized domain of hardware description language code generation.
  • The findings contribute to improving automated code generation by understanding the intricate interactions between model reasoning, specialization, and prompt engineering methods.

Computer Science > Hardware Architecture

arXiv:2603.08715 (cs)
[Submitted on 4 Feb 2026]

Title:VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation

View a PDF of the paper titled VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation, by Luca Collini and 4 other authors
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Abstract:Rapid advances in language models (LMs) have created new opportunities for automated code generation while complicating trade-offs between model characteristics and prompt design choices. In this work, we provide an empirical map of recent trends in LMs for Verilog code generation, focusing on interactions among model reasoning, specialization, and prompt engineering strategies. We evaluate a diverse set of small and large LMs, including general-purpose, reasoning, and domain-specific variants. Our experiments use a controlled factorial design spanning benchmark prompts, structured outputs, prompt rewriting, chain-of-thought reasoning, in-context learning, and evolutionary prompt optimization via Genetic-Pareto. Across two Verilog benchmarks, we identify patterns in how model classes respond to structured prompts and optimization, and we document which trends generalize across LMs and benchmarks versus those that are specific to particular model-prompt combinations.
Comments:
Subjects: Hardware Architecture (cs.AR); Computation and Language (cs.CL)
Cite as: arXiv:2603.08715 [cs.AR]
  (or arXiv:2603.08715v1 [cs.AR] for this version)
  https://doi.org/10.48550/arXiv.2603.08715
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arXiv-issued DOI via DataCite

Submission history

From: Luca Collini [view email]
[v1] Wed, 4 Feb 2026 01:52:30 UTC (357 KB)
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