Computer Science > Hardware Architecture
arXiv:2603.08719 (cs)
[Submitted on 10 Feb 2026]
Title:SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation
Authors:Mu-Chi Chen, Yu-Hung Kao, Po-Hsuan Huang, Shao-Chun Ho, Hsiang-Yu Tsou, I-Ting Wu, En-Ming Huang, Yu-Kai Hung, Wei-Po Hsin, Cheng Liang, Chia-Heng Tu, Shih-Hao Hung, Hsiang-Tsung Kung
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Abstract:Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctness and often rely on commercial models or external verification tools, which introduces concerns regarding cost, data privacy, and limited guarantees of functional correctness. This work proposes a unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification, enabling locally fine-tuned LLMs, SiliconMind-V1, to iteratively generate, test, and debug Register-Transfer Level (RTL) designs through test-time scaling. Experimental results on representative benchmarks (VerilogEval-v2, RTLLM-v2, and CVDP) demonstrate that the proposed approach outperforms the state-of-the-art QiMeng-CodeV-R1 in functional correctness while using fewer training resources.
| Subjects: | Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Software Engineering (cs.SE) |
| ACM classes: | I.2.2; I.2.6; I.2.7; J.6 |
| Cite as: | arXiv:2603.08719 [cs.AR] |
| (or arXiv:2603.08719v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2603.08719
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View a PDF of the paper titled SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation, by Mu-Chi Chen and 11 other authors
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