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Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU

arXiv cs.AI / 3/11/2026

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Key Points

  • Design Conductor (DC) is an autonomous agent capable of designing semiconductors from concept to tape-out ready GDSII layout files.
  • In 12 hours, DC autonomously built multiple micro-architecture variations of a RISC-V CPU (VerCore) that operates at 1.48 GHz and achieves a CoreMark score of 3261, comparable to a 2011 Intel Celeron SU2300.
  • This is the first known instance of an autonomous agent building a complete, functioning CPU from a high-level requirements document to finalized chip layout without human intervention.
  • The report details the design process including RTL implementation, testbench development, frontend debugging, timing optimization, and backend integration.
  • The authors discuss potential improvements for frontier models to enhance autonomous chip design and share insights on the future of chip manufacturing driven by such autonomous systems.

Computer Science > Hardware Architecture

arXiv:2603.08716 (cs)
[Submitted on 6 Feb 2026]

Title:Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU

View a PDF of the paper titled Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU, by The Verkor Team: Ravi Krishna and 2 other authors
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Abstract:Design Conductor (DC) is an autonomous agent which applies the capabilities of frontier models to build semiconductors end-to-end -- that is, from concept to verified, tape-out ready GDSII (layout CAD file). In 12 hours and fully autonomously, DC was able to build several micro-architecture variations of a complete RISC-V CPU (which we dub VerCore) that meet timing at 1.48 GHz (rv32i-zmmul; using the ASAP7 PDK), starting from a 219-word requirements document. The VerCore achieves a CoreMark score of 3261. For historical context, this is roughly equivalent to an Intel Celeron SU2300 from mid-2011 (which ran at 1.2 GHz). To our knowledge, this is the first time an autonomous agent has built a complete, working CPU from spec to GDSII. This report is organized as follows. We first review DC's design and its key components. We then describe the methodology that DC followed to build VerCore -- including RTL implementation, testbench implementation, frontend debugging, optimization to achieve timing closure, and interacting with backend tools. We review the key characteristics of the resulting VerCore. Finally, we highlight how frontier models could improve to better enable this application, and our lessons learned as to how chips will be built in the future enabled by the capabilities of systems like DC.
Subjects: Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI)
Cite as: arXiv:2603.08716 [cs.AR]
  (or arXiv:2603.08716v1 [cs.AR] for this version)
  https://doi.org/10.48550/arXiv.2603.08716
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arXiv-issued DOI via DataCite

Submission history

From: Suresh Krishna [view email]
[v1] Fri, 6 Feb 2026 18:05:06 UTC (5,557 KB)
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