TOPCELL: Topology Optimization of Standard Cell via LLMs

arXiv cs.LG / 4/17/2026

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Key Points

The paper presents TOPCELL, a scalable framework that tackles transistor topology optimization in standard cell design by reframing topology search as a generative task using LLMs.
It fine-tunes the approach with Group Relative Policy Optimization (GRPO), explicitly aligning generated topologies with both logical (circuit) constraints and spatial (layout) constraints.
Experiments in an industrial flow for an advanced 2nm technology node show TOPCELL finds routable, physically aware topologies that outperform foundation models.
When plugged into a SOTA automation workflow for 7nm library generation, TOPCELL achieves zero-shot generalization, matches exhaustive solvers’ layout quality, and delivers an 85.91× speedup.
The work targets the long-standing computational bottleneck of exhaustive topology exploration as circuit complexity grows in advanced nodes.

Abstract

Transistor topology optimization is a critical step in standard cell design, directly dictating diffusion sharing efficiency and downstream routability. However, identifying optimal topologies remains a persistent bottleneck, as conventional exhaustive search methods become computationally intractable with increasing circuit complexity in advanced nodes. This paper introduces TOPCELL, a novel and scalable framework that reformulates high-dimensional topology exploration as a generative task using Large Language Models (LLMs). We employ Group Relative Policy Optimization (GRPO) to fine-tune the model, aligning its topology optimization strategy with logical (circuit) and spatial (layout) constraints. Experimental results within an industrial flow targeting an advanced 2nm technology node demonstrate that TOPCELL significantly outperforms foundation models in discovering routable, physically-aware topologies. When integrated into a state-of-the-art (SOTA) automation flow for a 7nm library generation task, TOPCELL exhibits robust zero-shot generalization and matches the layout quality of exhaustive solvers while achieving an 85.91x speedup.