Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models

arXiv cs.AI / 4/27/2026

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Key Points

  • The paper proposes a multi-layer co-design approach that accelerates multimodal foundation models by jointly optimizing transformer blocks across both hardware and software.
  • It reduces compute and memory costs via hierarchy-aware mixed-precision quantization and structural pruning, targeting transformer blocks and MLP channels.
  • It speeds up inference using speculative decoding, small-to-large model cascading with lightweight self-tests, and co-optimization of sequence length, visual resolution/stride, and graph-level operator fusion.
  • It includes hardware-aware dataflow optimization and memory-efficient attention to satisfy on-chip bandwidth and latency budgets, supported by a specialized accelerator for transformer workloads.
  • Experiments on medical multimodal foundation models and code-generation tasks show effectiveness, with future extensions toward energy-efficient spiking multimodal foundation models.

Abstract

This work presents a multi-layered methodology for efficiently accelerating multimodal foundation models (MFMs). It combines hardware and software co-design of transformer blocks with an optimization pipeline that reduces computational and memory requirements. During model development, it employs performance enhancements through fine-tuning for domain-specific adaptation. Our methodology further incorporates hardware and software techniques for optimizing MFMs. Specifically, it employs MFM compression using hierarchy-aware mixed-precision quantization and structural pruning for transformer blocks and MLP channels. It also optimizes operations through speculative decoding, model cascading that routes queries through a small-to-large cascade and uses lightweight self-tests to determine when to escalate to larger models, as well as co-optimization of sequence length, visual resolution & stride, and graph-level operator fusion. To efficiently execute the model, the processing dataflow is optimized based on the underlying hardware architecture together with memory-efficient attention to meet on-chip bandwidth and latency budgets. To support this, a specialized hardware accelerator for the transformer workloads is employed, which can be developed through expert design or an LLM-aided design approach. We demonstrate the effectiveness of the proposed methodology on medical-MFMs and on code generation tasks, and conclude with extensions toward energy-efficient spiking-MFMs.