Semiconductors · Photonics
It isn't the chip.
It's the optical wiring.
Chinese GPU startup Biren announced an "optical supernode" that swaps not the compute die but the fabric between the dies for photonic interconnect. Where in NVIDIA's NVLink / NVSwitch moat is Biren pushing? A diagrammed read.
What Biren Announced
Inside the "optical supernode"
Biren Technology unveiled a new "supernode" for lashing together its GPUs at scale, and its differentiator is not the compute die but a photonic interconnect between the dies. Historically, AI training clusters have scaled through NVIDIA's copper NVLink and NVSwitch inside a rack (8–72 GPUs) and Ethernet / InfiniBand beyond it. Biren's proposal is to optically collapse that first tier so a larger cluster of GPUs presents itself as "one machine."
The move shifts the debate away from single-die specs (TFLOPS, HBM bandwidth) — where the H100 / B200 comparison sits — toward rack-scale aggregate bandwidth and latency. It targets exactly the terrain NVIDIA has been holding with NVLink Fusion and its co-packaged optics roadmap.
By The Numbers
The unit of comparison changes
Why It Matters Now
Why the fight is now about wiring
As frontier GPUs narrow the per-die gap, the winner is decided by how many you can lash together, how tightly.
Since NVIDIA's GB200 NVL72 in 2024 (72 GPUs bound into one machine by NVLink), industry attention has shifted rapidly to how to build the "giant one." Training parallelism is dominated by all-to-all GPU communication, and that is exactly where copper bandwidth and reach cap out. Fewer switch tiers, longer reach: optical interconnect is one of the only ways to lift the physical ceiling.
The broader context: with the U.S. Bureau of Industry and Security restricting NVIDIA's top-bin parts from Chinese buyers, Chinese vendors can't win on per-die performance. Biren instead attacks a layer where the delta is smallest — the wiring. If it can ship a rack-scale optical fabric before NVIDIA fully productizes in-rack optics, it can partly offset the export-control asymmetry — that's the bet.
Who Should Do What
How this hits, by role
This looks like a "Chinese GPU" story but it is really about a shift in the comparison axis. It lands differently by role.
Infra engineers: rewrite the RFP
Add explicit columns to your cluster RFP beyond TFLOPS and HBM: GPUs per "one machine," all-to-all bandwidth, copper vs. optical, out-of-rack reach. Same 8-GPU box can vary by tens of percent in effective throughput depending on how it's stitched, so unit price alone will mislead.
Execs & PMs: revisit China-region plans
Anything AI-serving hosted inside China will keep being designed without NVIDIA's top-bin parts. As domestic stacks differentiate at the network layer (Biren's approach), the option space of "regulated but not underpowered" expands. Worth folding into China-facing product roadmaps.
Individuals & small teams: limited direct effect
For local inference, CUDA + NVIDIA remains the pragmatic default. But if Chinese vendors gain share upstream — training the open-weight models you'll run — public base models may increasingly be optimized without NVIDIA assumptions. Keep the multi-vendor inference stack in mind medium term.
What Comes Next
Short-term outlook and moves
Three near-term expectations. (a) NVIDIA pulls in the volume plan for Co-Packaged Optics, and the rack-scale optical race hits gear-two. (b) Inside China, Biren, Huawei (Ascend), and Cambricon lean harder into "non-CUDA, non-NVIDIA" co-design. (c) Beyond training, optical interconnect becomes a differentiator for inference clusters, changing the price / kWh-per-perf axis. Two recommended actions: add a "definition of one machine" line to your RFP, and don't lock China-region designs to CUDA only.
The fight isn't at the chip anymore.
It's the fight to make a rack look like one machine.
Counterpoint
Limits and things easy to miss
It's premature to read this as pure upside. First, optical interconnect is still shallow in real-world operations across cost, reliability, thermals, and power; the true TCO surfaces only after years of production use. That is exactly why NVIDIA is being deliberate about CPO ramp timing. Second, Biren sits on the U.S. Entity List; with limits on advanced lithography and HBM supply, the largest bottleneck is steady volume of the compute die itself. "We announced it" and "we ship at scale" are separated by a very long distance.
One more thing: software. Even if the fabric works, the training stacks above it (PyTorch, Megatron, vLLM) are optimized around NVIDIA. The real test is how close NCCL-alternative implementations get on MoE and large-scale parallelism. The hardware announcement grabs the headline, but the next six months will be judged by two boring numbers: how many real training jobs land on the Biren stack, and how the MoE scaling curve looks in practice.