Computer Science > Hardware Architecture
arXiv:2603.08722 (cs)
[Submitted on 12 Feb 2026]
Title:ALADIN: Accuracy-Latency-Aware Design-space Inference Analysis for Embedded AI Accelerators
View a PDF of the paper titled ALADIN: Accuracy-Latency-Aware Design-space Inference Analysis for Embedded AI Accelerators, by T. Baldi and 2 other authors
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Abstract:The inference of deep neural networks (DNNs) on resource-constrained embedded systems introduces non-trivial trade-offs among model accuracy, computational latency, and hardware limitations, particularly when real-time constraints must be satisfied. This paper presents ALADIN, an accuracy-latency-aware design-space inference analysis framework for mixed-precision quantized neural networks (QNNs) targeting scratchpad-based AI accelerators. ALADIN enables the evaluation and analysis of inference bottlenecks and design trade-offs across accuracy, latency, and resource consumption without requiring deployment on the target platform, thereby significantly reducing development time and cost.
The framework introduces a progressive refinement process that transforms a canonical QONNX model into platform-aware representations by integrating both platform-independent implementation details and hardware-specific characteristics. ALADIN is validated using a cycle-accurate simulator of a RISC-V based platform specialized for AI workloads, demonstrating its effectiveness as a tool for quantitative inference analysis and hardware-software co-design. Experimental results highlight how architectural decisions and mixed-precision quantization strategies impact accuracy, latency, and resource usage, and show that these effects can be precisely evaluated and compared using ALADIN, while also revealing subtle optimization tensions.
| Comments: | |
| Subjects: | Hardware Architecture (cs.AR); Artificial Intelligence (cs.AI); Machine Learning (cs.LG) |
| Cite as: | arXiv:2603.08722 [cs.AR] |
| (or arXiv:2603.08722v1 [cs.AR] for this version) | |
| https://doi.org/10.48550/arXiv.2603.08722
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